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V23814-K1306-M230
Parallel Optical Link: PAROLITM Tx DC/MUX-ENC
V23815-K1306-M230
Parallel Optical Link: PAROLITM Rx DC/DEMUX-DEC
Preliminary
Dimensions in (mm) inches
(58.1) 2.287 Reference point for case temperature measurement (center of fin width) (1.5) .059 A A--A (1.5) .059 (7 .5) .295 (14) .551
(.13) (6.8) .268 .005 (1.3 max) .051 max (13.5) 0.531 (22.7) .894 (0.27) 4xM2 .011 (7) .276 (33.89) 1.334 A
.118
(3)
(12.73) .501 (1.2) .047 (1.0) .039
(14.9) .587 (17 .705 .9)
.098
(2.5)
APPLICATIONS
Telecommunication
* Switching equipment * Access network
Data Communication
* * * *
Interframe (rack-to-rack) Intraframe (board-to-board) On board (optical backplane) Interface to SCI and HIPPI 6400 standards
Absolute Maximum Ratings FEATURES * Power supply (3.3 V) * Low voltage differential signal electrical interface (LVDS) * 22 electrical data + 1 clock channels * Synchronous, DC-coupled optical link * 12 optical data channels * Electrical transmission data rate of 200-500 Mbit/s per channel, total link data rate up to 11 Gbit/s * Two clocking modes can be selected * Transmission distance depends on data rate and fiber skew, up to 75 m at maximum data rate * Transmitter: 840 nm VCSEL (Vertical Cavity Surface Emitting Laser) technology * Receiver: 840 nm PIN diode array * Fiber ribbon: 62.5 m graded index multimode fiber * MT based optical port * SMD technology * Transmitter: Class 1 FDA and Class 3A IEC laser safety compliant Stress beyond the values stated below may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Supply Voltage (VCC-VEE) .................................... -0.3 V to 4.5 V Data/Control Input Levels (VIN)(1) ................ -0.5 V to VCC+0.5 V LVDS Input Differential Voltage (|VID|)(2) .............................. 2.0 V Operating Case Temperature (TCASE)(3) ............... 0C to 80C Storage Ambient Temperature (TSTG )................ -20C to 100C Operating Moisture ............................................... 20% to 85% Storage Moisture .................................................... 20% to 85% Soldering Conditions Temp/Time (TSOLD, tSOLD)(4) ....260C/10s ESD Resistance (all pins to VEE human body model)(5) ....... 1 kV
Notes 1. At LVDS and LVCMOS inputs. 2. |VID|=|(input voltage of non-inverted input minus input voltage of inverted input)|. 3. Measured at case temperature reference point (see dimensional drawing). 4. Hot bar soldering. 5. To avoid electrostatic damage the handling precautions as for MOS devices must be taken into account.
Semiconductor Group
NOVEMBER 1998
DESCRIPTION PAROLI is a parallel optical link for high-speed data transmission. A complete PAROLI system consists of a transmitter module, a 12-channel fiber optic cable, and a receiver module. Transmitter V23814-K1306-M230 The PAROLI transmitter module converts parallel electrical input signals (data and clock) into parallel optical output signals. Figure 1. Transmitter block diagram
Electrical Inputs 22 Data Inputs Clock Input 22 Input Stage 11 Multiplexer Laser Encoder Frame Driver PLL Module Active 11 VCSEL Array 11 Optical Outputs Data Fibers Frame Fiber #1
strobed. Inputs 1 to 11 are routed before inputs 12 to 22. 4B words are then fed through eleven separate 4B/5B encoders to form the signals to be transmitted over the optical interface. Coding is based on the running disparity of previously transmitted output data. With a running disparity >0, either more High than Low levels or an equal number of Highs and Lows have been transmitted. The next output nibble will be inverted if High levels again dominate; otherwise it will be sent without inversion. With a running disparity <0, more Low than High levels have been transmitted. The next output nibble will be inverted if Low levels again dominate; otherwise it will be sent uninverted. To indicate whether a nibble has been inverted, an inversion bit is added, thus forming a 5B word (High, if transmitted nibble is uninverted; Low, if transmitted nibble is inverted). It is placed in front of the nibble (at the beginning of the 5B word) and immediately follows the FRAME transition. FRAME signal transitions delimit 5B words. Each 5B word contains the inversion bit and the nibble (inverted or non-inverted) mounted from two input data strobe cycles. The 5B words and FRAME signal are the signals transmitted over the optical interface. The pulse lengths of the 5B word and the frame signal is twice the pulse length of the electrical input signal. Example
Laser Active
LE -LE Laser Enable
-RESET
CLK_SEL
All electrical data and clock inputs are LVDS compatible. The module also features several LVCMOS compatible control inputs and outputs, which are described in the Transmitter Pin Description. The module features multiplexing and encoding of 22 electrical data input channels to 11 optical data output channels. The input data are serialized by 2 to 1 multiplexers which results in a reduced data rate at the electrical interface. The multiplexed data are encoded (4B5B encoding) to achieve DC-balanced signals at the input of the laser driver. The electrical input clock signal is used to control an integrated PLL circuit, which generates internal clock signals for encoding and multiplexing. The PLL circuit also generates a frame signal for the optical interface, which is transmitted over a separate fiber. Transmission delay of the PAROLI system is at a maximum of 4 strobe cycles + 3 ns for the transmitter, 3 strobe cycles + 3 ns for the receiver and approximately 5 ns per meter for the fiber optic cable. Clocking Modes The transmitter can be operated in one of two input clocking modes: Strobe mode or SCI mode. The mode is selected via CLK_SEL input. In Strobe mode, the rising edges of the noninverted clock signal are centered over the data bits. In SCI mode, High/Low transitions of clock and data signals coincide In SCI mode, the transmitter`s electrical interface complies with SCI and HIPPI standards. See Timing diagram Fig. 2. Multiplexing and Encoding The electrical input data is strobed into the input register with the internal clock signal generated by the PLL and then multiplexed 2:1. Input channels 1 to 11 are grouped with input channels 12 to 22, i.e. data inputs 1 and 12 feed optical data output 1; data inputs 2 and 13 feed optical data output 2, etc. Four data bits read from two input channels during two strobe cycles form 4B words. Inside the 4B word, data from the lower inputs (1 to 11) is transmitted first, i.e. after input data is
Semiconductor Group 2
To transmit electrical data at the maximum data rate of 500 Mbit/s per channel the corresponding clock signal (square 0101 pattern) has a frequency of 250 MHz in SCI mode or 500 MHz in STROBE mode. The FRAME signal with a corresponding frequency of 125 MHz is transmitted via fiber #1. The data rate of the optical signal at the Transmitter output is 1.25 Gbit/s in each of the fibers #2 to #12. LASER SAFETY The transmitter of the DC coupled Parallel Optical Link (PAROLI) is an FDA Class 1 laser product. It complies with FDA regulations 21 CFR 1040.10 and 1040.11. The transmitter is an IEC Class 3A laser product as defined by IEC 825-1. To avoid possible exposure to hazardous levels of invisible radiation, do not exceed maximum ratings. The PAROLI module must be operated under the specified operating conditions (supply voltage between 3.0 V and 3.6 V, case temperature between 0C and 80C) under all circumstances to ensure laser safety. Caution
Do not stare into beam or view directly with optical instruments. The use of optical instruments with this product will increase eye hazard.
Note Any modification of the module will be considered an act of "manufacturing," and will require, under law, recertification of the product under FDA (21 CFR 1040.10 (i)).
Laser Emission
Indication of laser aperture and beam
V23814/15-K1306-M230 Parallel Optical Link: PAROLITM Tx/Rx DC
START-UP PROCEDURE Detailed information can be found in the data sheet of the Paroli Testboard AC/DC, part number V23814-S1306-M931 and V23815-S1306-M931. * Switch system power supply on * Release -RESET when VCC has reached 3.0 V level and clock input is stable * Activate LE/-LE (laser enable) control input. * Delay tSTARTUP until laser controller and PLL have settled * After tSTARTUP MU and MA will be high , * Apply data input Module starts transmitting TECHNICAL DATA The electro-optical characteristics described in the following tables are valid only for operation under the recommended operating conditions. Recommended Operating Conditions
Parameter Power Supply Voltage Noise on Power Supply(1) Noise on Power Supply(2) LVDS Input Voltage Range(3) LVDS Input Differential Voltage(3, 4) LVDS Clock Input Rise/Fall Time(5) LVCMOS Input High Voltage LVCMOS Input Low Voltage LVCMOS Input Rise/ Fall Time(6) Clock Input Frequency, SCI Mode(7) Clock Input Frequency, Strobe Mode(7) Clock Input Duty Cycle Distortion Input Skew between Clock Inputs(8) Clock Input Total Jitter(pk-pk)
Notes Voltages refer to VEE=0 V. 1. Noise frequency is 1 kHz to 1 MHz. Voltage is peak-to-peak value. 2. Noise frequency is 1 MHz to 1 GHz. Voltage is peak-to-peak value.
3. Level diagram:
mV 1900 |VID| 500
Time
4. |VID|=|(input voltage of non-inverted input minus input voltage of inverted input)|. 5. See Measurement Conventions (Figure 3). 6. Measured between 0.8 V and 2.0 V. 7. Lower limit of clock frequency due to PLL frequency limitations. 8. See Measurement Conventions (Figure 3).
Transmitter Electro-Optical Characteristics
Parameter Symbol lCC P DRSCI DRSTR RIN VLVCMOSOL VLVCMOSOH 2.5 ILVCMOSI ILVCMOSOH ILVCMOSOL |II| -500 500 0.5 4.0 5.0 A mA 80 120 0.4 V 200 Min. Typ. 940 3.9 Max. Units 1140 mA 4.1 500 W Mbit/s Supply Current Power Consumption Data Rate in SCI Mode(1) Data Rate in Strobe Mode(1) LVDS Differential Input Impedance(2) LVCMOS Output Voltage Low LVCMOS Output Voltage High LVCMOS Input Current High/Low LVCMOS Output Current High(3) LVCMOS Output Current Low(4) LVDS Differential Input Current
Notes
Symbol VCC NPS1 NPS2 VLVDSI |VID| tR , tF VLVCMOSIH VLVCMOSIL tR , tF fCLOCK fCLOCK dcd tSPN CJ
Min. 3.0
Max. 3.6 10 100
Units V mV
500 100 100 2.0 VEE
1900 1000 400 VCC 0.8 20 ns MHz MHz % ps V
100 200 45
250 500 55
0.75 x ps tR, tF 0.025 UI
1. Data rate on electrical channel. Number of consecutive high or low bits is unlimited. 2. LVDS Input stage.
VCC Data In P Rin/2 Rin/2 Data In N 8K
3. Source current 4. Sink current
14 K 1.2 V 0.2 V C
Semiconductor Group 3
V23814/15-K1306-M230 Parallel Optical Link: PAROLITM Tx/Rx DC
Parameter Optical Rise Time(1) Optical Fall Time(1) (14)(2) Random Jitter
Symbol tR tF JR JD PAVG PSD C RIN ER
Min.
Max. 400 0.23 0.20
Units ps
Reset Timing Diagram
3.6 V 3.0 V VCC
UI
-RESET
Deterministic jitter Launched Average Power Launched Power Shutdown Center Wavelength Spectral Width (FWHM) Relative Intensity Noise Extinction Ratio (dynamic)
Notes
2.0 V of VCC 0.8 V of VCC t3
-11
-6.0 -30
dBm
Data data invalid t1 data valid t2
820
860 2.0 -116
nm dB/Hz dB Parameter -RESET On Delay Time(1) -RESET Off Delay Time -RESET Low Duration(2)
Notes
Symbol Min. Typ. Max. Units t1 t2 t3 tbd 100 50 ms s ms
5.0
Optical parameters valid for each channel. 1. 20%-80% level. 2. Measured with 01010... (square) optical output pattern.
1. Valid after the release of -RESET. (Clock input must first be stable. Keep -RESET low until clock input is at stable frequency.) 2. Only when not used as power-on reset. At any failure recovery, -RESET should be brought to low level for at least t3.
Figure 2. Timing diagram Strobe Mode
P Clock In N Data In 1...22 t1 t2 Crossing Level |VID| min.
Figure 3. Measurement conventions for LVDS signals Setup and Hold Times
P Clock N Data Crossing Level |VID| min.
Parameter Input Setup Time(1) Input Hold Time(1)
Note
Symbol t1 t2
Min. 250
Typ.
Max. Units ps
tSETUP tHOLD
Setup and hold times are measured between the crosspoint of positive and negative clock and the points where rising and falling data edge cross the borders of the V-range.
1. Refers to positive clock input signal. See Measurement Conventions (Figure 3).
Rise and fall times / Skew
tskew P (or N)
SCI Mode
P Clock In N Data In 1...22 tS tS |VID| min.
tfall trise N (or P) |VID| min.; |VOD| min.
Parameter Input Skew(1)
Symbol tS
Min. Typ. Max.
Units ps
Transmitter Pin Description
Pin# 1 2 3 4 5 Pin Name VCC1 t.b.l.o. Level/Logic Description Power supply voltage of laser driver to be left open
. Maximum Input Skew=(2*Data Rate)-1 - 250 ps - DCDIN-CLOCK where DCDIN-CLOCK=|(Data Rate)-1-dcd*(1/2 Data Rate)-1|(dcd: see Recommended Operating Conditions). Note 1. See Measurement Conventions (Figure 3).
Semiconductor Group 4
V23814/15-K1306-M230 Parallel Optical Link: PAROLITM Tx/Rx DC
Pin# 6
Pin Name LA
Level/Logic LVCMOS Out
Description Laser Active High=laser controller is operational Ground Ground Power supply voltage of digital circuitry and PLL
Pin# 48 49 50 51 52 53 54 55 56 57 58 59 60 61
Pin Name VCC3 DI09N DI09P DI20N DI20P DI10N DI10P DI21N DI21P DI11N DI11P DI22N DI22P CLK-SEL
Level/Logic
Description Power supply voltage of digital circuitry and PLL
LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVCMOS In
Data Input #9, inverted Data Input #9, non-inverted Data Input #20, inverted Data Input #20, non-inverted Data Input #10, inverted Data Input #10, non-inverted Data Input #21, inverted Data Input #21, non-inverted Data Input #11, inverted Data Input #11, non-inverted Data Input #22, inverted Data Input #22, non-inverted Input Clocking Mode Select High=strobe mode Low=SCI mode This input has an internal pullup resistor. When left open, strobe mode is active. to be left open Power supply voltage of digital circuitry and PLL
7 8 9 10
VEE VEE VCC3 MA LVCMOS Out
Module Active High=normal operation Low=laser fault or PLL not locked or -RESET low Clock Input, inverted Clock Input, non-inverted Data Input #1, inverted Data Input #1, non-inverted Data Input #12, inverted Data Input #12, non-inverted Data Input #2, inverted Data Input #2, non-inverted Data Input #13, inverted Data Input #13, non-inverted Data Input #3, inverted Data Input #3, non-inverted Data Input #14, inverted Data Input #14, non-inverted Power supply voltage of digital circuitry and PLL
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
CIN CIP DI01N DI01P DI12N DI12P DI02N DI02P DI13N DI13P DI03N DI03P DI14N DI14P VCC3 DI04N DI04P VEE DI15N DI15P DI05N DI05P DI16N DI16P DI06N DI06P DI17N DI17P DI07N DI07P DI18N DI18P DI08N DI08P VEE DI19N DI19P
LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In
62 63 64
t.b.l.o. VCC3 -RESET LVCMOS In low active
LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In LVDS In
Data Input #4, inverted Data Input #4, non-inverted Ground Data Input #15, inverted Data Input #15, non-inverted Data Input #5, inverted Data Input #5, non-inverted Data Input #16, inverted Data Input #16, non-inverted Data Input #6, inverted Data Input #6, non-inverted Data Input #17, inverted Data Input #17, non-inverted Data Input #7, inverted Data Input #7, non-inverted Data Input #18, inverted Data Input #18, non-inverted Data Input #8, inverted Data Input #8, non-inverted Ground Data Input #19, inverted Data Input #19, non-inverted 69 70 71 72 t.b.l.o. t.b.l.o. t.b.l.o. VCC1 68 -LE LVCMOS In low active 65 66 67 VEE VEE LE LVCMOS In
High=normal operation Low=resets module, shuts laser diode array down This input has an internal pulldown resistor to ensure laser safety switch-off in case of unconnected -RESET input. Ground Ground Laser ENABLE. High=laser array is on if -LE is also active. Low=laser array is off. This input can be used for connection with an Open Fiber Control (OFC) circuit to enable IEC class 1 links. Has an internal pull-up, therefore can be left open. Laser ENABLE. Low=laser array is on if LE is also active. This input can be used for connection with an Open Fiber Control (OFC) circuit to enable IEC class 1 links. Has an internal pulldown, therefore can be left open. to be left open to be left open to be left open Power supply voltage of laser driver
Semiconductor Group 5
V23814/15-K1306-M230 Parallel Optical Link: PAROLITM Tx/Rx DC
DESCRIPTION Receiver V23815-K1306-M230 The PAROLI receiver module converts parallel optical input signals (data and frame) into parallel electrical output signals. Figure 4. Receiver block diagram
Optical Inputs Data 11 Fibers Frame Fiber 11 Pin Diode Array 11 Electrical Outputs 22 22 Data Decoder Outputs AmpliDemultiOutput fier plexer Stage Frame Clock Clock PLL Output OE FRAME_DET -RESET LOCK_DET CLK_SEL
ENSD -SD11
The 4B words from the decoders are then demultiplexed 1:2 to electrical output data channels. Output channels 1 to 11 are grouped with output channels 12 to 22, i.e. optical data input 1 feeds electrical data outputs 1 and 12; optical data input 2 feeds electrical data outputs 2 and 13, etc. Demultiplexing of a 4B word (with bits #1...#4) takes two data output cycles. During the first cycle, bit #1 is presented at the lower data output (1...11) and bit #2 at the higher data output (12...22). During the second cycle, bits #3 and #4 are presented at the lower and higher outputs, respectively. (Example: Of the 4B word from optical data channel 1, bit #1 is presented at corresponding lower data output 1 and bit #2 is presented at corresponding higher data output 12.) The demultiplexed data bits are presented as 22 parallel outputs together with the output clock signal, the characteristics of which depend on the clocking mode. (See Clocking Modes above.) Start-up Procedure Detailed information can be found in the data sheet of the Paroli Testboard AC/DC, part number V23815-S1306-M931. * Switch system power supply on * Release -RESET when VCC has reached 3.0 V level * Wait for LOCK_DET to become High * Module starts presenting data at the data outputs if OE is High. If OE is at a high level or left open during start-up, clock output will start running immediately after release of -RESET. Clock frequency will drift upwards to the operating frequency established by FRAME input when FRAME_DET indicates sufficient input signal level. After PLL has locked (indicated by LOCK_DET high level) data outputs are also enabled. OE can be used for complete LVDS switch-off whenever clock drift during start-up is critical.
All electrical data and clock inputs are LVDS compatible. The module also features several LVCMOS compatible control inputs and outputs, which are described in the Receiver Pin Description. The module features demultiplexing and decoding of 11 optical data input channels to 22 electrical data output channels. The frame signal is used to control an integrated PLL circuit, which generates internal clock signals for decoding and demultiplexing. The PLL circuit also generates a clock signal at the Receiver output. Transmission delay of the PAROLI system is at a maximum of 4 strobe cycles + 3 ns for the transmitter, 3 strobe cycles + 3 ns for the receiver and approximately 5 ns per meter for the fiber optic cable. Clocking Modes The receiver can be operated in one of two output clocking modes: Strobe mode or SCI mode. The mode is selected via CLK_SEL input. In Strobe mode, the rising edges of the noninverted clock signal are centered over the data bits. In SCI mode, High/Low transitions of clock and data signals coincide In SCI mode the electrical interface complies with SCI and HIPPI standards. See Timing diagram Fig. 5. Decoding and Demultiplexing The input data received from the optical interface is strobed into the input register with the PLL generated internal clock signal. The data is read in relation to FRAME input. The input frequency expected at FRAME is one fifth of square input data frequency, as FRAME transitions indicate 5B word boundaries. FRAME input is expected to change levels simultaneously with data transitions. All eleven input data channels are fed through individual 5B/4B decoders. Decoding is based on an inversion bit which is received at the first position of a 5B word. This bit determines whether the nibble received at bit positions 2, 3, 4 and 5 has to be inverted. An inversion bit High level indicates a nibble which was transmitted uninverted, i.e. this 4B nibble will be directly forwarded to the demultiplexer. If the inversion bit received is Low, the corresponding nibble will be inverted by the decoder before it is demultiplexed.
Semiconductor Group 6
V23814/15-K1306-M230 Parallel Optical Link: PAROLITM Tx/Rx DC
TECHNICAL DATA Recommended Operating Conditions
Parameter Power Supply Voltage Noise on Power Supply(1) Noise on Power Supply(2) Differential LVDS Termination Impedance LVCMOS Input High Voltage LVCMOS Input Low Voltage LVCMOS Input Rise/ Fall Time(3) Optical FRAME Input Frequency Optical Data, FRAME Input Skew(4) Optical FRAME Input Duty Cycle Distortion Optical Data, FRAME Input Rise/Fall Time(5) Optical Data, FRAME Input Extinction Ratio Input Center Wavelength
Notes Voltages refer to VEE=0 V. 1. Noise frequency is 1 kHz to 1 MHz. Voltage is peak-to-peak value. 2. Noise frequency is 1 MHz to 1 GHz. Voltage is peak-to-peak value. 3. Measured between 0.8 V and 2.0 V. 4. Between all data and frame optical inputs. 5. 20%-80% level.
Receiver Electro-Optical Characteristics
Parameter Min. 3.0 Max. 3.6 10 100 80 2.0 VEE 120 VCC 0.8 20 50 125 tbd tbd 400 5.0 820 860 % ps dB nm ns MHz V Units V mV Supply Current Power Consumption LVDS Output Low Voltage(1, 4) LVDS Output High Voltage(1, 4) LVDS Output Differential Voltage(1, 2, 4) LVDS Output Offset Voltage(1, 3, 4) Clock Output Rise and Fall Time(5) LVCMOS Output Voltage Low LVCMOS Output Voltage High LVCMOS Input Current High/Low LVCMOS Output Current High(6) LVCMOS Output Current Low(7) Data Rate per channel (output) Clock Frequency SCI Mode Clock Frequency Strobe Mode
Notes 1. Level Diagram:
Symbol lCC P VLVDSOL VLVDSOH |VOD |
Min.
Typ. Max. 910 3.0 1030 3.7
Units mA W mV
Symbol VCC NPS1 NPS2 Rt VLVCMOSIH VLVCMOSIL tR, tF fFRAME tSI dcd tR, tF ER C
925 1475 250 400
VOS tR, tF VLVCMOSOL
1125
1275 400 400
mV ps mV
VLVCMOSOH 2500
ILVCMOSI ILVCMOSOH ILVCMOSOL DR fCLOCK fCLOCK 200 100 200 -500 500 0.5 4.0 500 250 500 Mbit/s MHz MHz A mA
mV 1475 |VOD| 925
Time
2. |VOD|=|(output voltage of non-inverted output minus output voltage of inverted output)|. 3. VOS=1/2 (output voltage of inverted output + output voltage of noninverted output). 4. LVDS output must be differentially terminated with Rt. 5. With a maximum capacity load of 5 pF See Measurement . Conventions (Figure 6). 6. Source current. 7. Sink current
.
Semiconductor Group 7
V23814/15-K1306-M230 Parallel Optical Link: PAROLITM Tx/Rx DC
Parameter Sensitivity (Average Power)(1) Saturation (Average Power) FRAME Detect Assert Level(2) FRAME Detect Deassert Level(2) FRAME Detect Hysteresis(2) Return Loss of Receiver
Notes
Symbol PIN PSAT PFDA PFDD PFDA - PFDD ARL
Min.
Max. -18.0
Units dBm
FRAME_DET and -RESET Timing Diagrams
Optical FRAME Input
-8.0
FRAME_DET
t1 0.4 V t3
t2 2.5 V t4
-19.0 -26.0 1.0 12
-RESET 0.8 V LOCK_DET
4.0
dB
2.0 V t5 Data Low Clock Low t6 t7
Optical parameters valid for each channel. 1. BER=10 -12 at infinite ER. 2. PFDA: Average optical power when FRAME_DET switches from Low to High. PFDD: Average optical power when FRAME_DET switches from High to Low. Values are also applicable for SD11 function, except SD11 is low active.
Data and Clock Out
valid
valid
OE
2.0 V 0.8 V Data Low Clock Low t8 t9
Figure 5. Timing diagram Strobe Mode
P Clock Out N Data Out 1...22 t1 t2 Crossing Level |VOD| min.
Data and Clock Out
valid
valid
Parameter FRAME_DET Deassert time(1)
Symbol t1 t2 t3 t4
Min.
Max. 10
Units s
Parameter Output Setup Time Output Hold Time
Symbol t1 t2
Min. Typ. Max. 625
Units ps
FRAME_DET Assert Time(1) FRAME_DET Low to LOCK_DET Low Delay FRAME_DET High to LOCK_DET High Duration(2) -RESET Low Duration(3) -RESET Off Delay Time
20 tbd
ns
SCI Mode
P Clock Out N Data Out 1...22 tS tS |VOD| min.
t5 t6 t7 t8 t9
tbd 20 tbd 20 20
ms ns ms ns
-RESET On Delay Time(4) LVDS Output Disable Time LVDS Output Enable Time
In this operation mode the clock output is supplied in phase to data outputs.
Notes 1. Timing also applicable for SD11 function on fiber #12. 2. Stable frame input required. -RESET not activated. 3. Except when used as power-on reset. At any failure recovery, -RESET should be brought to low level for at least t3. 4. Valid if -RESET is set high when VCC exceeds 3.0 V level and optical FRAME (FRAME_DET=high) and data input is valid. t5 starts when all these conditions are fulfilled. -RESET must be set to Low during power-up.
Parameter Output Skew(1)
Note
Symbol ts
Min. Typ. Max. 810
Units ps
1. All data outputs and clock output.
Semiconductor Group 8
V23814/15-K1306-M230 Parallel Optical Link: PAROLITM Tx/Rx DC
Figure 6. Measurement conventions for LVDS signals Setup and Hold Times
P Clock N Data tSETUP tHOLD Crossing Level |VOD| min.
Pin# 16 17 18 19 20 21 22 23 24 25 26 27
Pin Name DO12N DO02P DO02N DO13P DO13N DO03P DO03N DO14P DO14N VCC4 DO04P DO04N VEE DO15P DO15N DO05P DO05N DO16P DO16N DO06P DO06N DO17P DO17N DO07P DO07N DO18P DO18N DO08P DO08N VEE DO19P DO19N VCC4 DO09P DO09N DO20P DO20N DO10P DO10N DO21P DO21N DO11P DO11N DO22P DO22N
Level/Logic Description LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out Data Output #12, inverted Data Output #2, non-inverted Data Output #2,inverted Data Output #13, non-inverted Data Output #13, inverted Data Output #3, non-inverted Data Output #3, inverted Data Output #14, non-inverted Data Output #14, inverted Power supply voltage of decoder LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out Data Output #4, non-inverted Data Output #4, inverted Ground Data Output #15, non-inverted Data Output #15, inverted Data Output #5, non-inverted Data Output #5, inverted Data Output #16, non-inverted Data Output #16, inverted Data Output #6, non-inverted Data Output #6, inverted Data Output #17, non-inverted Data Output #17, inverted Data Output #7, non-inverted Data Output #7, inverted Data Output #18, non-inverted Data Output #18, inverted Data Output #8, non-inverted Data Output #8, inverted Ground Data Output #19, non-inverted Data Output #19, inverted Power supply voltage of decoder LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out Data Output #9, non-inverted Data Output #9, inverted Data Output #20, non-inverted Data Output #20, inverted Data Output #10, non-inverted Data Output #10, inverted Data Output #21, non-inverted Data Output #21, inverted Data Output #11, non-inverted Data Output #11, inverted Data Output #22, non-inverted Data Output #22, inverted
Setup and hold times are measured between the crosspoint of positive and negative clock and the points where rising and falling data edge cross the borders of the V-range. Rise and Fall Times / Skew
tskew P (or N)
28 29 30 31 32
|VID| min.; |VOD| min.
tfall trise
N (or P)
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Receiver Pin Description
Pin# 1 2 3 4 5 Pin Name VEE VCC1 VCC2 t.b.l.o. -RESET Level/Logic Description Ground Power supply voltage of preamplifier Power supply voltage of analog circuitry to be left open LVCMOS in High=receiver is active. low active Low=internal logic is reset and LVDS outputs are set to low. Internal pull- up pulls to high level when this input is left open. LVCMOS Out High=FRAME input signal present (on fiber #1) Low=insufficient FRAME signal Power supply voltage of digital circuitry Ground Power supply voltage of decoder LVCMOS Out High=PLL has successfully locked onto incoming FRAME signal. LOCK_DET being low sets all LVDS data outputs to low; clock output is unaffected by LOCK_DET. Clock Output, non-inverted Clock Output, inverted Data Output #1, non-inverted Data Output #1, inverted Data Output #12, non-inverted
6
FRAME_ DET
7 8 9 10
VCC3 VEE VCC4 LOCK_ DET
11 12 13 14 15
COP CON DO01P DO01N DO12P
LVDS Out LVDS Out LVDS Out LVDS Out LVDS Out
Semiconductor Group 9
V23814/15-K1306-M230 Parallel Optical Link: PAROLITM Tx/Rx DC
Pin# 61
Pin Name CLK_SEL
Level/Logic Description LVCMOS In Input Clocking Mode Select High=strobe mode Low=SCI mode This input has an internal pullup resistor. When left open, strobe mode is active. LVCMOS In High=enable LVDS outputs Low=set LVDS outputs (data and clock) to static low level. Internal pull-up pulls to high level when input is left open to be left open Power supply voltage of decoder Ground Power supply voltage of digital circuitry LVCMOS Out low active Signal Detect Optical Data Channel 11 (on fiber #12) Low=signal of sufficient AC power is present on fiber # 12 High=signal on fiber # 12 is insufficient
Cleaning and Soldering Process for Transmitter and Receiver Special care must be taken to remove residuals from the soldering and washing process, which can impact the mechanical function. Avoid the use of aggressive organic solvents like ketones, ethers, etc. Consult the supplier of the PAROLI modules and the supplier of the solder paste and flux for recommended cleaning solvents. The following common cleaning solvents will not affect the module: deionized water, ethanol, and isopropyl alcohol. Airdrying is recommended to a maximum temperature of 100C. Do not use ultrasonics. During soldering, heat must be applied to the leads only, to ensure that the case temperature never exceeds 100C. The module must be mounted with a hot-bar soldering process using a SnPb solder type, e.g.. S-Sn63Pb37E, in accordance with ISO 9435. Figure 7. Numbering convention
Pin 28 Pin 29 Pin 1
62
OE
63 64 65 66 67
t.b.l.o. VCC4 VEE VCC3 -SD11
Top View
Fiber 1 Fiber 12
68
ENSD
LVCMOS In High=SD11 and FRAME_DET function enabled. Low=FRAME_DET and SD11 is set to permanent active. PLL is then forced to start lock-on procedure (for test purposes). Internal pull-up pulls to high level when input is left open. to be left open Power supply voltage of analog circuitry Power supply voltage of preamplifier Ground
Pin 44 Pin 45
Pin 72
69 70 71 72
t.b.l.o. VCC2 VCC1 VEE
Optical Port * Designed for Siemens Simplex MT Connector (SMC) * Port outside dimensions: 15.4 mm x 6.8 mm (width x height) * MT compatible fiber spacing (250 m) and alignment pin spacing (4600 m) * Alignment pins fixed in module port * Integrated mechanical keying * Process plug (SMC dimensions) included with every module * Cleaning of port and connector interfaces necessary prior to mating Features of Siemens Simplex MT Connector (SMC) (as part of optional PAROLI fiber optic cables) * Uses standardized MT ferrule * MT compatible fiber spacing (250 m) and alignment pin spacing (4600 m) * Snap-in mechanism * Ferrule bearing spring loaded * Not strain-relieved * Integrated mechanical keying
Semiconductor Group 10
V23814/15-K1306-M230 Parallel Optical Link: PAROLITM Tx/Rx DC
Figure 8. Recommended footprint: receiver Dimensions in mm (inches)
(18) .709
Figure 9. Recommended footprint: transmitter Dimensions in mm (inches)
(18) .709
Top View (13.5) .531 (0.2) A B .008 A B (20.1) .08.004
Top View (13.5) .531 (0.2) A B .008 A B (20.1) .08.004
(22.7) .894
(15.4) .606 (3.5) .138
(15.4) .606 (3.5) .138 (22.7) .894
(7).276
(7).276
(33.89) 1.334 .55) (0.65 = 17 27x .0256=.691
72
(33.89) 1.334 .55) (0.65 = 17 .0256=.691
1
72
27x 29 44
1
28
28
Detail Y
45
29
44
Detail Y
(1.64) .065
45
(1.64) .065
B A
(0.65 = 9.75) 15 x .0256=.691 (14.9) .587
B 15 x A
(0.65 = 9.75) .0256=.691
(14.9) .587 (18.7) .736
(18.7) .736
Dashed lines show module outline and board space required for SMC plug. No electronic components on customer PCB within this area.
Dashed lines show module outline and board space required for SMC plug. No electronic components on customer PCB within this area.
Figure 10. Mounting hole, Detail Y
(2.575) .1014 (1.80.05) .071.002 72x 29 (2.55+0.03/-0) 0.100+.001/-0 (0.05) M A B 4x (0.35+0.05/-0) .014+.002/-0 72x
(2.775) .0109
28
(0.05) M A B .002 M A B
(0.05) M A B .002 M A B
.002 M A B
dashed lines show module outlines
Semiconductor Group 11
V23814/15-K1306-M230 Parallel Optical Link: PAROLITM Tx/Rx DC
Figure 11. Applications
LVDS
PAROLI LD Tx
SMC Port
Link Controller
Rx PD Ribbon Cable
Board-to-Board
Passive Optical Backplane
PAROLI Tx Rx SMC Port Ribbon Cable Backplane Connector I/O Board Optical Feed Through
Backplane
PAROLI LD SMC Port SMC Port PD
Tx LVDS
Ribbon Cable
Rx LVDS
Point-to-Point
Siemens Semiconductor Group * Fiber Optics * Wernerwerkdamm 16 * Berlin D-13623, Germany Siemens Microelectronics, Inc. * Optoelectronics Division * 19000 Homestead Road * Cupertino, CA 95014 USA Siemens K.K. * Fiber Optics * Takanawa Park Tower * 20-14, Higashi-Gotanda, 3-chome, Shinagawa-ku * Tokyo 141, Japan www.siemens.de/semiconductor/products/37/376.htm (Germany) * www.smi.siemens.com/opto/fo/fo.html (USA)

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